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? semiconductor components industries, llc, 2001 may, 2001 rev. 5 1 publication order number: mc74ac652/d mc74ac652, mc74act652 octal transceiver/register with 3-state outputs (non-inverting) the mc74ac/act652 consists of registered bus transceiver circuits, with outputs, dtype flipflops and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. data on the a or b bus will be loaded into the respective registers on the lowtohigh transition of the appropriate clock pin (cab or cba). the four fundamental data handling functions available are illustrated in figures 1 to 4. ? independent registers for a and b buses ? multiplexed realtime and stored data transfers ? choice of true and inverting data paths ? 3state outputs ? 300 mil slim dualinline package ? outputs source/sink 24 ma ? act652 has ttl compatible inputs http://onsemi.com marking diagrams device package shipping ordering information mc74ac652n pdip24 15 units/rail mc74ac652dw soic24 30 units/rail mc74act652n pdip24 15 units/rail MC74AC652DWR2 soic24 1000 tape & reel mc74act652dw soic24 30 units/rail mc74act652dwr2 soic24 1000 tape & reel a = assembly location l, wl = wafer lot y, yy = year w, ww = work week pdip24 n suffix case 724 so24 dw suffix case 751e act652 awlyyww 1 24 mc74act652n awlyyww 1 24 pdip24 so24 mc74ac652n awlyyww ac652 awlyyww transfer from register to bus reg reg abus bbus real time transfer abus to bbus reg reg abus bbus real time transfer bbus to abus reg reg abus bbus figure 1. figure 2. storage from bus to register reg reg abus bbus figure 3. figure 4.
mc74ac652, mc74act652 http://onsemi.com 2 pin assignment pin function a 0 a 7 data register a inputs data register a outputs b 0 b 7 data register b inputs data register b outputs cab, cba clock pulse inputs sab, sba transmit/receive inputs gab, gba output enable inputs figure 6. logic symbol figure 7. logic diagram b 0 b 1 b 2 b 3 b 4 b 5 a 0 a 1 a 2 a 3 a 4 a 5 a 6 b 6 b 7 a 7 cab sab gab cba sba gba d 0 c 0 d 0 c 0 cab sba cba sab gab gba b 0 a 0 1 of 8 channels to 7 other channels note: this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. figure 5. pinout: 24lead plastic package (top view) 23 24 22 21 20 19 18 2 1 34567 v cc 17 8 16 9 15 10 cba sba gba b 0 b 1 b 2 b 3 b 4 b 5 cab sab gab a 0 a 1 a 2 a 3 a 4 a 5 a 6 14 11 13 12 b 6 b 7 a 7 gnd
mc74ac652, mc74act652 http://onsemi.com 3 function table inputs data i/o* operation or f nction gab gba cab cba sab sba a 0 a 7 b 0 b 7 operation or function l h h or l h or l x x in p ut in p ut isolation l h ? ? x x i npu t i npu t store a and b data x h ? h or l x x input unspecified* store a, hold b h h ? ? x** x input output store a in both registers l x h or l ? x x unspecified* input hold a, store b l l ? ? x x** output input store b in both registers l l x x x l out p ut in p ut real-time b data to a bus l l x h or l x h o u t pu t i npu t stored b data to a bus h h x x l x in p ut out p ut real-time a data to b bus h h h or l x h x i npu t o u t pu t stored a data to b bus h l horl horl h h out p ut out p ut stored a data to b bus and h l h or l h or l h h o u t pu t o u t pu t stored a data to b bus and stored b data to a bus *the data output functions may be enabled or disabled by various signals at the gba and gab inputs. data input functions are always enabled; i.e., data at the bus pins will be stored on every low-to-high transition of the appropriate clock inputs. **select control = l: clocks can occur simultaneously. h = high voltage level; l = low voltage level; x = immaterial; ? = low-to-high transition maximum ratings* symbol parameter value unit v cc dc supply voltage (referenced to gnd) 0.5 to +7.0 v v in dc input voltage (referenced to gnd) 0.5 to v cc + 0.5 v v out dc output voltage (referenced to gnd) 0.5 to v cc + 0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage t emperature 65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recom- mended operating conditions. recommended operating conditions symbol parameter min typ min unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 v cc v v cc @ 3.0 v 150 t r , t f input rise and fall time (note 1) ac devices exce p t schmitt in p uts v cc @ 4.5 v 40 ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v 25 tt f input rise and fall time (note 2) v cc @ 4.5 v 10 ns/v t r , t f in ut rise and fall time (note 2) act devices except schmitt inputs v cc @ 5.5 v 8.0 ns/v t j junction temperature (pdip) 140 c t a operating ambient temperature range 40 25 85 c i oh output current e high 24 ma i ol output current e low 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac652, mc74act652 http://onsemi.com 4 dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = 40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input v oltage 4.5 2.25 3.15 3.15 v or v cc 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input v oltage 4.5 2.25 1.35 1.35 v or v cc 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = 50 m a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 2.56 2.46 v 12 ma 4.5 3.86 3.76 v i oh 24 ma 5.5 4.86 4.76 24 ma v ol minimum low level 3.0 0.002 0.1 0.1 i out = 50 m a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 0.36 0.44 v 12 ma 4.5 0.36 0.44 v i ol 24 ma 5.5 0.36 0.44 24 ma i in maximum input 55 01 10 m a v i = v cc , gnd leakage current 5.5 0 . 1 1 . 0 m a icc , i ozt maximum v i (oe) = v il , v ih 3-state 5.5 0.6 6.0 m a v i = v cc , gnd current v o = v cc , gnd i old 2minimum dynamic ot tc t 5.5 75 ma v old = 1.65 v max i ohd output current 5.5 75 ma v ohd = 3.85 v min i cc maximum quiescent 55 80 80 m a v in = v cc or gnd q supply current 5.5 8 . 0 80 m a in cc *all outputs loaded; thresholds on input associated with output under test. 2maximum test duration 2.0 ms, one input loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v.
mc74ac652, mc74act652 http://onsemi.com 5 ac characteristics 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = 40 c to +85 c c l = 50 pf unit min max min max t plh propagation delay 3.0 4.0 17.0 3.0 19.0 ns t plh gy cpba or cpab to a n or b n 5.0 2.5 12.0 2.0 14.0 ns t phl propagation delay 3.0 3.0 14.5 2.5 16.5 ns t phl gy cpba or cpab to a n or b n 5.0 2.0 10.5 1.5 12.0 ns t plh propagation delay 3.0 3.0 14.0 2.5 16.0 ns t plh gy a or b to b n or a n 5.0 2.0 9.5 1.5 11.0 ns t phl propagation delay 3.0 2.5 13.0 2.0 15.0 ns t phl gy a or b to b n or a n 5.0 1.5 9.0 1.0 10.5 ns t plh propagation delay 3.0 3.0 14.0 2.5 16.0 ns t plh gy sba or sab to a n or b n 5.0 2.5 10.0 2.0 11.5 ns t phl propagation delay 3.0 2.5 13.5 2.0 15.5 ns t phl gy sba or sab to a n or b n 5.0 2.0 10.0 1.5 11.5 ns t pzh output enable time 3.0 2.5 12.0 2.0 13.5 ns t pzh oeba to a n 5.0 1.5 9.0 1.0 10.0 ns t pzl output enable time 3.0 2.5 12.0 2.0 14.0 ns t pzl oeba to a n 5.0 1.5 9.0 1.0 10.5 ns t phz output disable time 3.0 3.0 13.0 2.5 14.0 ns t phz oeba to a n 5.0 2.0 11.0 1.5 12.0 ns t plz output disable time 3.0 2.5 12.5 2.0 14.0 ns t plz oeba to a n 5.0 2.0 10.5 1.5 12.0 ns *voltage range 3.3 v is 3.3 v 0.3 v. voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac652, mc74act652 http://onsemi.com 6 dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = 40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input v oltage 5.5 1.5 2.0 2.0 v or v cc 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input v oltage 5.5 1.5 0.8 0.8 v or v cc 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = 50 m a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 3.86 3.76 v i oh 24 ma 5.5 4.86 4.76 i oh 24 ma v ol minimum low level 4.5 0.001 0.1 0.1 v i out = 50 m a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 0.36 0.44 v i oh 24 ma 5.5 0.36 0.44 i oh 24 ma i in maximum input 55 01 10 m a v i = v cc , gnd leakage current 5.5 0 . 1 1 . 0 m a icc , d i cct additional max. i cc /input 5.5 0.6 1.5 ma v i = v cc 2.1 v i ozt maximum v i (oe) = v il , v ih 3-state 5.5 0.6 6.0 m a v i = v cc , gnd current v o = v cc , gnd i old 2minimum dynamic ot tc t 5.5 75 ma v old = 1.65 v max i ohd output current 5.5 75 ma v ohd = 3.85 v min i cc maximum quiescent 55 80 80 m a v in = v cc or gnd q supply current 5.5 8 . 0 80 m a in cc *all outputs loaded; thresholds on input associated with output under test. 2maximum test duration 2.0 ms, one input loaded at a time.
mc74ac652, mc74act652 http://onsemi.com 7 ac characteristics 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = 40 c to +85 c c l = 50 pf unit min max min max t plh propagation delay 50 40 14 5 35 16 5 ns t plh pro agation delay cpba or cpab to a n or b n 5. 0 4 . 0 14 .5 3 .5 16 .5 ns t phl propagation delay 50 35 14 5 30 16 5 ns t phl pro agation delay cpba or cpab to a n or b n 5. 0 3 .5 14 .5 3 . 0 16 .5 ns t plh propagation delay 50 25 11 5 20 13 0 ns t plh pro agation delay a or b to b n or a n 5. 0 2 .5 11 .5 2 . 0 13 . 0 ns t phl propagation delay 50 25 11 5 20 13 0 ns t phl pro agation delay a or b to b n or a n 5. 0 2 .5 11 .5 2 . 0 13 . 0 ns t plh propagation delay 50 25 12 0 20 13 5 ns t plh pro agation delay sba or sab to a n or b n 5. 0 2 .5 12 . 0 2 . 0 13 .5 ns t phl propagation delay 50 30 12 0 25 13 5 ns t phl pro agation delay sba or sab to a n or b n 5. 0 3 . 0 12 . 0 2 .5 13 .5 ns t pzh output enable time 50 20 11 5 15 13 0 ns t pzh out ut enable time oeba to a n 5. 0 2 . 0 11 .5 1 .5 13 . 0 ns t pzl output enable time 50 25 11 5 20 13 0 ns t pzl out ut enable time oeba to a n 5. 0 2 .5 11 .5 2 . 0 13 . 0 ns t phz output disable time 50 30 13 0 25 14 0 ns t phz out ut disable time oeba to a n 5. 0 3 . 0 13 . 0 2 .5 14 . 0 ns t plz output disable time 50 25 12 5 20 14 0 ns t plz out ut disable time oeba to a n 5. 0 2 .5 12 .5 2 . 0 14 . 0 ns t pzh output enable time 50 25 12 0 20 13 5 ns t pzh out ut enable time oeab to b n 5. 0 2 .5 12 . 0 2 . 0 13 .5 ns t pzl output enable time 50 25 12 0 20 13 5 ns t pzl out ut enable time oeab to b n 5. 0 2 .5 12 . 0 2 . 0 13 .5 ns t phz output enable time 50 35 13 5 30 14 5 ns t phz out ut enable time oeab to b n 5. 0 3 .5 13 .5 3 . 0 14 .5 ns t plz output enable time 50 30 13 5 25 15 0 ns t plz out ut enable time oeab to b n 5. 0 3 . 0 13 .5 2 .5 1 5. 0 ns t s setup time, high or low 50 70 80 ns t s setu time, high or low a n or b n to cpba or cpab 5. 0 7. 0 8 . 0 ns t h hold time, high or low 50 25 25 ns t h hold time, high or low a n or b n to cpba or cpab 5. 0 2 .5 2 .5 ns t w cpab, cpba pulse width 50 60 70 ns t w cpab, cpba pulse width high or low 5. 0 6 . 0 7. 0 ns *voltage range 3.3 v is 3.3 v 0.3 v. voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter 74act typ unit test conditions c in input capacitance 4.5 pf v cc = 5.0 v c i/o input/output capacitance 15 pf v cc = 5.0 v c pd power dissipation capacitance 60.0 pf v cc = 5.0 v
mc74ac652, mc74act652 http://onsemi.com 8 package dimensions pdip24 n suffix 24 pin plastic dip package case 72403 issue d notes: 1. chamfered contour optional. 2. dimension l to center of leads when formed parallel. 3. dimensioning and tolerancing per ansi y14.5m, 1982. 4. controlling dimension: inch. a b 24 13 12 1 t seating plane 24 pl k e f n c d g m a m 0.25 (0.010) t 24 pl j m b m 0.25 (0.010) t l m note 1 dim min max min max millimeters inches a 1.230 1.265 31.25 32.13 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.020 0.38 0.51 e 0.050 bsc 1.27 bsc f 0.040 0.060 1.02 1.52 g 0.100 bsc 2.54 bsc j 0.007 0.012 0.18 0.30 k 0.110 0.140 2.80 3.55 l 0.300 bsc 7.62 bsc m 0 15 0 15 n 0.020 0.040 0.51 1.01 so24 dw suffix 24 pin plastic soic package case 751e04 issue e notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. a b p 12x d 24x 12 13 24 1 m 0.010 (0.25) b m s a m 0.010 (0.25) b s t t g 22x seating plane k c r x 45 m f j dim min max min max inches millimeters a 15.25 15.54 0.601 0.612 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.41 0.90 0.016 0.035 g 1.27 bsc 0.050 bsc j 0.23 0.32 0.009 0.013 k 0.13 0.29 0.005 0.011 m 0 8 0 8 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029
mc74ac652, mc74act652 http://onsemi.com 9 notes
mc74ac652, mc74act652 http://onsemi.com 10 notes
mc74ac652, mc74act652 http://onsemi.com 11 notes
mc74ac652, mc74act652 http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into t he body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc74ac652/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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